In the field of digital modules operating in networks, a basic operational function involves the transfer of data between the interconnected digital modules. During the course of data transfer, it is necessary to keep account of the amount of data being transferred and to insure that the data has been transferred with integrity on a reliable basis.
As seen in FIG. 2A, one generalized type of data transfer system involves the transfer of data between the host processor 4 and peripheral units such as disk drive units 70. The data transfer operations are seen to be transferred through a channel interface module 8.sub.c which then transfers the data to the device interface module 8.sub.d which can then communicate with the peripheral units 70 both for the output of data to the peripheral units and for the receipt of data from the peripheral units.
FIG. 2B shows a semi-detailed drawing of the device interface module 8.sub.d indicating that a memory buffer for temporary holding data being transferred can communicate with a SCSI Peripheral Controller SPC 80 in order to handle the transfers of data between the peripheral 70 and the memory buffer 24.sub.d. During the course of data transfer along the bus 6, an integrity circuit 81 will continuously monitor the transfer of data and insure that the integrity of data transferred is valid.
FIG. 3 shows a more detailed view of the network which was basically shown in FIG. 2A. Here in FIG. 3 multiple numbers of host computers 4.sub.a. . . 4.sub.d can communicate with channel interface modules 8.sub.c1 and 8.sub.c2. Each channel interface module has a buffer memory 24.sub.c1 and 24.sub.c2 which can temporarily hold data for transfer through two ports 31.sub.c and 32.sub.c.
The two ports 31.sub.c and 32.sub.c are connected to dual system busses 6.sub.a and 6.sub.b which enable any host computer 4 to communicate through either one of the channel interface modules and then through either one of the dual ports 31.sub.c -32.sub.c onto the system buses 6.sub.a and 6.sub.b which enables data transfers to be passed on through multiple numbers of device interface modules, such as 8.sub.d1 and 8.sub.d2.
The device interface module 8.sub.d1 and 8.sub.d2 each have a buffer memory 24.sub.d1 and 24.sub.d2 which is connected through a multiplexor 24.sub.x1 and 24.sub.x2 on through multiple channels (6.sub.0, 6.sub.1, 6.sub.2, 6.sub.3) to a set of four I/O ports designated as SCSI Protocol Controllers SPC.sub.0, (80.sub.0), SPC.sub.1, (80.sub.1), SPC.sub.2, (80.sub.2), and SPC.sub.3, (80.sub.3). It is then seen that the peripheral devices 70.sub.a. . . 70.sub.d each can have dual I/O port connections to two sets of device interface modules. Thus, by allowing communication through two ports, there is also provision for communication to any one port should one of the other ports fail.
As seen in FIG. 5A, a block of data composed of "X" bytes will have a header portion which provides the address and destination of commands and includes information as to the size of the block. After the header, there is present the main bulk of the data block followed by a signature portion designated as the Error Detection Code (EDC) signature. The EDC signature is provided to characterize the value of the block of data and will represent the value of the data being transmitted in the main block.
Subsequently, as seen in FIG. 5B, there may be data block transfers of a different volume or size as shown by the block designated "Y" bytes. Here again the header will provide the address, destination commands, block size, and other pertinent data, after which the main portion holds the data to be transferred followed by the EDC (Error Detection Code) which characterizes the data being transferred.
When a block of data, such as that of "X" bytes or that of "Y" bytes, is being transferred, it is necessary that some means be provided to recognize the block size and insure that the integrity of the data transfer be validated. It is further necessary to monitor the data transfer to see that the entire preselected number of bytes has been transferred.
As seen in FIG. 6, there is shown an example of the transfer of two different block sizes to be transmitted between a sending and receiving digital module, the first block size being of 180 bytes with a header and EDC signature. This is followed by a larger block size of 512 bytes which also has its own personal header portion and succeeding EDC signature. The presently described system operates to insure that there will be no delay in the data transfer operation even though blocks of different sizes are being transferred and additionally, that the different block sizes will be concurrently checked on-the-fly for integrity without any delay to the data transfer operation.
As illustrated in FIG. 6, blocks of data to be transferred can occur in different block sizes. For example, the first block in FIG. 6 has a block size of 180 bytes and the second block has a size of 512 bytes. FIG. 6 also illustrates how the header contains information as to the block size and how the EDC signature provides a Hexspace of 36 bits. The first bit involves a parity check and the remaining number of bits are used to provide an original EDC signature. In the present system involving the four channel busses (6.sub.0, 6.sub.1, 6.sub.2, 6.sub.3) shown in FIG. 1, there is seen a device interface module 8.sub.d which has a buffer memory 24.sub.d holding data to be transferred between peripheral units (70.sub.p0. . . 70.sub.p3) and any one of the said host processor 4.sub.a. . . 4.sub.d of FIG. 3.
The presently described system of FIG. 1 provides a device interface module 8.sub.d which permits four concurrently operating channels between the buffer memory 24.sub.d and the peripheral units 70. Each channel is provided with its own integrity checking circuit Ic (81.sub.0, 81.sub.1, 81.sub.2, 81.sub.3) which operates on-the-fly and insures that the data transfer on that channel is a correct data transfer.